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Digital Design course cover

Digital Design

Gates to FIFOs, clock crossings and a working CPU. 68 lessons in 12 modules. Pick a module on the left. Videos on the right follow your choice.

Module 1: Numbers and logic

How hardware represents information and decides things.

  1. 1Binary, hex and two's complementWatch lecture
  2. 2Logic gates and truth tablesWatch lecture
  3. 3Boolean algebra and De MorganWatch lecture
  4. 4Karnaugh mapsWatch lecture
  5. 5What a gate is made of: CMOSWatch lecture

Module 2: Combinational building blocks

Outputs that depend only on the present inputs.

  1. 6MultiplexersWatch lecture
  2. 7Decoders and priority encodersWatch lecture
  3. 8Half, full and ripple addersWatch lecture
  4. 9Carry look-ahead and prefix addersWatch lecture
  5. 10Subtractors, comparators and an ALUWatch lecture
  6. 11Barrel shifters and glitchesLecture coming soon

Module 3: Verilog that means hardware

Describe circuits, and always picture the circuit you are describing.

  1. 12Modules, ports and hierarchyLecture coming soon
  2. 13wire, reg, logic and 4-state valuesLecture coming soon
  3. 14assign and always blocksLecture coming soon
  4. 15Blocking and non-blocking assignmentsLecture coming soon
  5. 16Accidental latchesLecture coming soon
  6. 17Parameters and generateLecture coming soon
  7. 18Your first self-checking testbenchLecture coming soon
  8. 19Reading waveforms like an engineerLecture coming soon

Module 4: Sequential logic

Circuits with memory, and the clock that disciplines them.

  1. 20SR and D latchesLecture coming soon
  2. 21The D flip-flopLecture coming soon
  3. 22Setup and hold: the two promisesLecture coming soon
  4. 23Synchronous and asynchronous resetsLecture coming soon
  5. 24Enables and clock gatingLecture coming soon
  6. 25Shift registersLecture coming soon
  7. 26LFSRsLecture coming soon

Module 5: Counters and frequency dividers

Timing generators found in nearly every block.

  1. 27Up, down and loadable countersLecture coming soon
  2. 28Ring, Johnson and Gray countersLecture coming soon
  3. 29Divide by 2, 4 and any even numberLecture coming soon
  4. 30Odd division with 50% duty cycleLecture coming soon
  5. 31Edge detectors and pulse generatorsLecture coming soon

Module 6: Finite state machines

The control logic behind almost every chip block.

  1. 32States, transitions and outputsLecture coming soon
  2. 33Moore and Mealy machinesLecture coming soon
  3. 34Writing FSMs: encoding and styleLecture coming soon
  4. 35Detecting 1101, with overlapLecture coming soon
  5. 36Non-overlapping detectionLecture coming soon
  6. 37Traffic light and vending machineLecture coming soon
  7. 38Debugging and safe FSMsLecture coming soon

Module 7: Memories and FIFOs

Moving and storing data between blocks.

  1. 39Register filesLecture coming soon
  2. 40Using SRAM in RTLLecture coming soon
  3. 41Synchronous FIFOLecture coming soon
  4. 42FIFO depth calculationLecture coming soon
  5. 43Valid/ready handshakesLecture coming soon
  6. 44Skid buffersLecture coming soon

Module 8: Arithmetic and datapaths

Making computation fast.

  1. 45Multipliers and Booth encodingLecture coming soon
  2. 46Fixed-point arithmeticLecture coming soon
  3. 47PipeliningLecture coming soon
  4. 48Retiming and area-speed trade-offsLecture coming soon

Module 9: Static timing

Why a chip has a maximum frequency.

  1. 49The timing pathLecture coming soon
  2. 50Clock skew and jitterLecture coming soon
  3. 51Fixing violationsLecture coming soon
  4. 52Constraints, false and multicycle pathsLecture coming soon

Module 10: Clock domain crossing

Safely crossing between unrelated clocks.

  1. 53Metastability and MTBFLecture coming soon
  2. 54The two-flop synchronizerLecture coming soon
  3. 55Pulse crossing fast to slowLecture coming soon
  4. 56Multi-bit transfers and handshakesLecture coming soon
  5. 57Gray code pointersLecture coming soon
  6. 58Asynchronous FIFOLecture coming soon
  7. 59Reset synchronizers and RDCLecture coming soon

Module 11: Designing for silicon

RTL that survives synthesis, lint and power reviews.

  1. 60What synthesis does to your codeLecture coming soon
  2. 61Lint and code qualityLecture coming soon
  3. 62Low-power RTLLecture coming soon
  4. 63ArbitersLecture coming soon

Module 12: Projects and interview preparation

Bring it all together, and prepare to be hired.

  1. 64Minor project: UART transmitter and receiverLecture coming soon
  2. 65Minor project: SPI controllerLecture coming soon
  3. 66Major project: small RISC-style CPULecture coming soon
  4. 67Industry project: streaming packet engineLecture coming soon
  5. 68Interview patternsLecture coming soon