Physical Design
Coming soonRTL to GDS: floorplan through signoff.
This course is being prepared. Start with Digital Design, which is live now, or practise on the Verilog problems.
What it will cover
- Floorplanning
- Power planning
- Placement
- Clock tree synthesis
- Routing
- ECO
- IR drop and EM
- Signoff
- Tapeout